1. Field of the Invention
This invention relates generally to electronic design automation (EDA) systems used for designing integrated circuits. The invention is more specifically related to a method for incrementally optimizing a circuit design using EDA synthesis and logic optimizing tools during the integrated circuit design process.
2. Description of the Prior Art
The design process for all integrated circuits is composed of several discrete operations. Initially, the proposed functionality for a circuit is analyzed by one or more chip designers. These designers define the logical components of the circuit and their interactions by specifying the logic design using design capture tools. These design capture tools are commonly implemented in software executing on an engineering workstation, with well-known input devices being used to receive design information from the chip designer, and output devices, such as computer displays, being used to provide visual feedback of the design to the designer as it is being constructed. Such software is typically implemented as part of an electronic design automation (EDA) system. Specifically, the design entry operation involves generating a description of the logic design to be implemented on the circuit chip in an appropriate machine-readable form. Chip designers generally employ hierarchial design techniques to determine the appropriate selection and interconnection of logic and/or memory devices which will enable the chip to perform the desired function. These techniques involve describing the chip's functionality at various levels of abstraction, ranging from the most general function performed by the chip to the precise functions performed by each logic and/or memory element on the chip.
A common method for specifying the integrated circuit design is the use of hardware description languages. This method allows a circuit designer to specify the circuit at the register transfer level (also known as a "behavior description"). Using this method, the circuit is defined in small building blocks. The names of the building blocks are specified by the circuit designer. Thus, they usually are logical names with specific functional meaning.
Encoding the design in a hardware description language (HDL) is a major design entry technique used to specify modern integrated circuits. Hardware description languages are specifically developed to aid a designer in describing a circuit. These languages often contain specific functions and syntax to allow complex hardware structures to be described in a compact and efficient way.
It is useful to distinguish between those components of an integrated circuit design called cells, provided by a silicon chip vendor as primitive cells (i.e., leaf candidates), and the user-defined hierarchy blocks built upon them. One way is to speak of a "cell library" vs. a "design library" as two separate libraries, both of which are available to subsequent designs. Alternatively, at least initially, a design library contains a cell library. A cell library is a database containing detailed specifications on the characteristics of each logical component available for use in a design. Initial cell library contents are usually provided by the chip vendor. The components in the cell library are identified by the generic description of the component type. For example, the term "NAND" for a NAND gate is its type description and distinguishes this component from others such as OR gates, flip-flops, multiplexors, and so on. A two-input NAND gate might be of type 2NAND. When a 2NAND component is specified as part of a given circuit design, it is given an instance name, to distinguish it from all other 2NAND gates used in the circuit. The instance name typically includes the instance names of all parent instances by concatenation when defining the instance in the context of the chip.
A single name is sufficient when dealing only in the context of a single user function. The user-defined blocks can then be used to design larger blocks of greater complexity. The user-defined blocks are added to the design library, which grows from the additions of new design modules as the design evolves. The top level of the design hierarchy may be a single block that defines the entire design, and the bottom layer of the hierarchy may consist of leaf cells, the cells (i.e., the logical components) that were originally provided in the cell library. The resulting design is often called a detailed (or gate-level) description of the logic design.
The generation of the detailed description is often accomplished by logic design synthesis software for HDL entry. The logic design synthesis software generates a gate-level description of user-defined input and output logic, and also creates new gate-level logic to implement user-defined logical functions. Constituent parts of new gate-level logic created during each pass through the logic design synthesis software are given computer-generated component and net names. Each time the logic design synthesis software is executed for the integrated circuit design, the component and net names which are generated by the software, and not explicitly defined by the user, may change, depending on whether new logic has been added to or deleted from the integrated circuit design. Typically, the logic design synthesis software is executed many times during the integrated circuit design process, because errors may be detected during the simulation and testing phases of the design cycle and then fixed in the behavioral description, or because the design is incomplete, etc.
The output of the design capture and synthesis tools is a logic design database which completely specifies the logical and functional relationships among the components of the design. Once the design has been converted into this form, it may be optimized by sending the logic design database to a logic optimizer tool implemented in software. The logic optimizer may remove logic from the design that is redundant or unnecessary. As discussed above, this action affects the component and net names generated by the logic synthesis tool.
It is also necessary to verify that the logic definition is correct and that the integrated circuit implements the function expected by the circuit designer and meets predetermined performance goals (e.g. timing). This verification is currently achieved by estimated timing and simulation software tools. The design undergoes design verification analysis in order to detect flaws in the design. The design is also analyzed by simulating the device resulting from the design to assess the functionality of the design. If errors are found or the resulting functionality is unacceptable, the designer modifies the behavior description as needed. These design iterations help to ensure that the design satisfies its requirements.
As a result of each design revision, the logic design synthesis-generated component and net names may completely change. Further, the precise changes made by the logic optimizer may not be known without a detailed analysis of the database. Thus, the EDA tools downstream in the design process must typically be re-executed on the entire design, and not just on the portions of the design that contained the change.
After timing verifications and functional simulation has been completed on the design, placement and routing of the design's components is performed. These steps involve allocating components of the design to locations on the integrated circuit chip and interconnecting the components to form nets. Finally, final timing verification is performed after placement and routing is complete.
A major problem that arises during the above design process is that the changes made by the logic optimizer during each design iteration may not be precisely known. Further, the complex gate-level names generated by the logic design synthesis software may change during each iteration of the design process because of modifications to the integrated circuit design. Even a minimal change at critical points in the integrated circuit design may cause the logic design synthesis tools to change a substantial amount of the circuit design, and may generate completely new names for substantially all of the design. As a result, other EDA tools such as the logic optimizing, placement and routing tools must be re-executed on the entire design, rather than on only the portions or modules of the design that have been changed. Since many of the steps in the design process are iterative, such small changes in the behavior description of the design, usually made as a result of finding errors during timing verification and simulation, may cause large amounts of processing time to be used for re-executing the optimizing, placement, and routing tools on the entire design. Designers may iterate literally hundreds of times through the design and test cycle. One skilled in the art can readily see that this situation causes a substantial increase in the time needed for integrated circuits to be designed and tested. For current integrated circuit designs having hundreds of thousands of gates, this situation is unacceptable.
An EDA process that also minimizes the number of iterations needed to arrive at an acceptable design solution would be a valuable advance in the state of the art. The desired method would allow a circuit designer to converge on an acceptable design solution in fewer iterations of the design cycle than under previous methods. As indicated above, existing methods operate on an entire circuit design, thereby resulting in placement modifications and changes in timing characteristics. In extreme cases, the circuit designer may go through many design iterations, fixing new design problems arising from each iteration without converging on an acceptable solution. A better approach would be to ensure that only those portions of the circuit design that have changed in the current design iteration are revisited by the logic optimization, placement, routing, and timing analysis tools. This approach would leave acceptable portions of the circuit design in a fixed state, thus allowing the designer to concentrate on finalizing the design for the remaining portions of the integrated circuit design.